Friday, July 27, 2012

[JimsJobs] (job) Power Integrations - IC Failure Analysis Engineer - San Jose, CA

 

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Candidates should apply online at: http://hire.jobvite.com/Jobvite/Jobvite.aspx?m=nA9vejwg as well as by email to Charles.Jo@powerint.com .

Best,

Charles Jo
650.906.2600 m





 

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IC Failure Analysis Engineer

Power Integrations is seeking an Applications Engineer with Failure Analysis focus and will be responsible for switching power systems development and applications engineering.





IC Failure Analysis Engineer

Power Integrations
San Jose, CA, United States
Regular Full-Time


 

The Failure Analysis Engineer will perform device level failure analysis to support RMA and customer issues.  Responsibilities include performing fault isolation and defect analysis/characterization on power IC's to identify root causes of product failures in power supply applications and/or in production test.  Provide comprehensive technical reports to customers on findings from product failure investigations.  Advise internal and external customers reagrding corrective actions based on the results of the analysis. 

 

Responsibility will also include effective verbal and written communication of results, which will be used to drive improvements in product design, process technology, and applications.  Such communication will require, but not limited to, writing cogent and convincing technical reports suitable for external customers.

 

REQUIREMENTS

 

BSEE or equivalent discipline is required.  MSEE is preferred.  At least 5 years of experience in failure analysis of power semiconductors, analog, and/or mixed signal devices.  Candidates should have hands-on experience in failure analysis, and electrical fault isolation and defect characterization tools and techniques such as the following: ATE, cureve trace, micro-probing, light emission microscopy, liquid crystal, CSAM, XRAY, FIB, SEM and deprocessing techniques.  In-depth understanding of both digital and analog circuits, device physics and IC fabrication processes.  Ability to interpret IC ATE test datalog is required.  Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required.  Good technical writing skills is required.





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