Our client is a fabless semiconductor startup that has developed a programmable analog signal processing platform that provides substantial gains in performance and reductions in power consumption and cost (by factors of over 10x), compared to digital signal processing platforms. The first suite of products from Our client, implemented in a standard CMOS process, is targeted at the wireless cellular infrastructure market and enables operators and system OEMs to deploy cellular networks at greatly reduced power, complexity, and cost.
Our client is currently a revenue-stage company with a growing roster of customers. It is privately held, and its investors include August Capital, Sevin Rosen, Kleiner Perkins, and Ridgewood Capital.
SENIOR ASIC DESIGN ENGINEER
Job Description
In this role, you will be responsible for Digital IP development for Our client’s IC team. You will be designing state-of-the-art baseband processors and working on improving our SoC architecture. You will be interacting closely with Communication Systems Engineers as well as Firmware, Verification, and Physical Design Engineers. The position involves execution of processes from micro-architecture all the way to the successful handoff of IP cores to our Physical Design and Verification Engineers. Our team is small but very efficient, and we rely heavily on custom automation of our processes, as demonstrated by our many home-built tools. If you are a solid logic designer that gets excited by signal processing applications, and you enjoy building robust and automatic process flows, then Our client is the right place for you!
Job Requirements
- BSEE/CE required; MS or PhD preferred
- A minimum of four consecutive years of relevant, professional experience
- Excellent logic design skills, demonstrated by successful SoC implementations in ASIC or FPGA
- Excellent understanding of SoC architectures for micro-controller based designs
- Experience with Digital Signal Processing or Baseband Processing is required; knowledge of computer architecture and pipelined designs is a plus
- Excellent knowledge of Verilog and popular EDA simulation, implementation and verification tools from Synopsys, Cadence, or Mentor-Graphics
- Experience with modeling DSP blocks with Matlab/Simulink is an advantage
- Good knowledge of scripting languages such as Python, Perl, CSH, or similar
- Good experience with state-of-the-art verification methodologies (RTL assertions, coverage, etc.)
- Well rounded and experienced with multiple aspects of ASIC implementation; willingness to support Verification, Lab and Back-End activities when necessary
- Excellent written and oral communication skills
Jon Ramos
Staffing Consultant
Marcom Choices Staffing
P.O. Box 620632
Woodside, Ca. 94062
408 887-0455
