Computing/Server/Storage Hardware Engineering Architect
Responsibilities/Descriptions:
Responsible for the hardware engineering architecture of high speed system, with links for short reach and long reach applications and high density to reach high performance. Understand the requirement and future trends of the industry, Capable of working with vendors, universities, and standard bodies in industry leading technologies. Define high speed architecture for next generation system, computing or/and switching to meet the system design requirements, and are able to assure 10 years of competitive strength:
- Define the architechture of the system, including chassis, and high speed solutions.
- Understand multi-gigabit serial links for backplane and chip-to-chip interfaces. Familiar with
the related industry high speed channel standard.
- Familiar with SerDes architecture and interconnect architecture, understand characterization of
SerDes , high speed connectors and package designs.
- Backplane channel end to end evaluation, familiar with the PCB and cable manufacture
capability and define the balance architecture for high speed channels in the system.
Qualifications/Requirements:
- Working experience in Computing / Core router / Edge router similar product in large
infrastructure company.
- Experience in co-designing of ASIC, Package, PCB and System interconnects is desired.
- Experience in hardware engineering design, computing and/or switching board.
- Understand DFX to reach the best competitive strength in life cycle.
- A MSEE, or a PhD is preferred, with 10 years of experience.
If interested, please just send your resume to;
(Know anyone like this? We appreciate referrals)
Contact;
Mark Apton
Futurewei Technologies - US R&D Center
http://www.linkedin.com/in/markapton
E-mail: mark.apton@huawei.com
2330 Central Expressway, Santa Clara, California, 95050
Phone: 408- 330-5338; Fax: 408-330-5089
www.usahuawei.com ($40B.)
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