Senior Physical Design Engineer-
In this position, the individual will be responsible for performing place and route at block and full chip level. Should be able to run verification and debug such as DRC, LVS, XOR at block and full chip level. Some experience on custom layout. Work with little supervision. Involve with tapeout activities such as checking full chip verifications. Prepare database, ftp...etc. Perform ECO in existing database. Good knowledge on the opus environment, VLE, VXL. Responsible for standard cell and macrocells libraries. Good communication skill and require very strong team player. Good knowledge on skill, perl, C languages.
To Apply:
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MARKETPLACE
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