Hi David;
Thank you for "replying all" on this email.... But since you did, I will follow suit.
The headline is misleading at best. A "shift in focus" is far from "pulling out...sales".
We just hired two more recruiters for the Sales and Marketing team.
I work for R&D and there is no need or plans to reduce in that dept.
Huawei has been taking worldwide market share from your company for years and will continue to do so.
Thanks,
Mark
-----Original Message-----
From: David Siadat (dsiadat) [mailto:dsiadat@cisco.com]
Sent: Thursday, April 25, 2013 11:56 AM
To: Mark Apton; 'JimsJobs@yahoogroups.com'; 'SMAA_jobs@yahoogroups.com'; 'hp_alumni_jobs@yahoogroups.com'; 'si-list@freelists.org'
Subject: RE: Sr. SI Engineer (10G+, Backplane Architect) needed at Huawei in Santa Clara, CA;
Mark,
Can you comment on the latest news impacting your local staffing?
http://techcrunch.com/2013/04/23/after-years-of-government-scrutiny-over-security-concerns-huawei-says-its-quitting-the-u-s/
Thanks,
David
-----Original Message-----
From: si-list-bounce@freelists.org [mailto:si-list-bounce@freelists.org] On Behalf Of Mark Apton
Sent: Thursday, April 25, 2013 11:38 AM
To: 'JimsJobs@yahoogroups.com'; 'SMAA_jobs@yahoogroups.com'; 'hp_alumni_jobs@yahoogroups.com'; 'si-list@freelists.org'
Subject: [SI-LIST] Sr. SI Engineer (10G+, Backplane Architect) needed at Huawei in Santa Clara, CA;
My Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle Engineer; Responsibilities/Description; Responsible for providing the backplane architecture and 10G+ High Speed SI solutions for Next Generation telecommunications equipment in the router, switch and transmission product lines to meet system design requirements.
Experience in co-designing of ASIC, Package, PCB and System interconnects desired. including:
- Design and analysis of multi-gigabit serial links for Backplane and
chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and
other standards.
- Familiar with ASIC, Hardware, interconnect teams to evaluate design
tradeoffs and optimize design performance / risk / cost /manufacturability.
- To evaluate package designs, characterization of SerDes, and design
experiments to do the same.
- Modeling of electromagnetic 3-D structures.
- Modeling and analyzing power delivery networks (PDN).
- Familiar with memory technologies such as DDR2/DDR3 is preferred.
Qualifications/Requirements:
- Must have significant, recent Backplane and SerDes experience.
- Performing physical measurements to collect data for design
validation and simulation correlations.
- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,
Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and
other tools.
- Experience in correlating simulation results with lab measurements
using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self
motivated with strong communication and teamwork skills.
- The working experience in Core router or Edge router similar product
in large telecomm infrastructure company.
A MSEE, or a PhD is preferred, with 10years of experience.
Some portion of time will be spent in Shenzhen working with the HQ SI team. Travel will be about 30-60% to China.
Please contact mark.apton@huawei.com<mailto:mark.apton@huawei.com>
----------------------------------------------------------
To unsubscribe from si-list:
si-list-request@freelists.org with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list
For help:
si-list-request@freelists.org with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
http://www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
| Reply via web post | Reply to sender | Reply to group | Start a New Topic | Messages in this topic (5) |
