| In this position, the individual will be responsible for Layout Document and database management, including archiving. Responsible for tape-out checks included reviewing and documenting all the post layout verification results and checksum results; this will serve as Tape-out QA prior to all tapeouts. Responsible for checking all errors (real and pseudo) by viewing the layout against the verification results, comparing the results with previous projects and working with layout team, design team and process team to determine the status and course of action/waivers. Automatic and manual checking all verifications results such as drc, lvs, xor, dummy fill, and dummy gen. Develop/enhance tapeout flow; this activity will involve automation of the check process after all post processing is completed and database is ready for tapeout. Responsible for sending/receiving data from SNDK/TSB including revision control. Work with layout/CAD/process team on special runset and design rule code development for memory array and pitch circuits. Responsible for management of checklist and review with the management team for all tape-outs. The individual will work on layer generation and optimize manually if needed and will write scripts for various layout daily activities. Responsibilities include running Hercules/Calibre LVS/DRC/XOR/layer generation and debug the results independently, working with CAD engineers and other mask designers to co-ordinate various CAD issues as it relates to layout, and responsible for database transfer to joint development partner including working with designers during this process. Person should have good attitude to adopt and learn new software as we migrate from Hercules. Document (as it relates to layout/design/CAD info from and to joint development partner) numbering and management system; this will also include documents provided to off-site design centers. Support full chip activities including tape-out and ECO management/control after initial tape-out. Support test structure development including structures necessary for design rule development and will work closely with layout manager & layout project and interface with designers and CAD engineers when necessary. For this role some layout experience is necessary and will require familiarity and experience with Cadence layout tools. Set up and coordinate meeting for all tapeout activities. Obtain all necessary approval for tapeout. Coordinate and communicate tapeout to offsite team and vendor. Work closely with layout manager & layout project lead. Independent thinking on assignment and able to provide suggestion to layout/CAD/process teams. Coordinate various activities with process, lithography, device, design, and CAD groups. This position requires a BA/BA degree with 6 months of certified layout training or equivalent experience and a minimum of 12 years experience. MS/MA preferred with some courses in VLSI CAD. Experience with Cadence "VLE, VXL,CCAR, PCELL" layout and schematic tools. Experience in Hercules/Calibre DRC/LVS verification tools. Experience in Unix & Linux environments. Software Skills: Skill language, Tcl, Perl, Python, C & C++. Needs to be able to debug DRC/LVS independently. Must be proficient in post layout processing, preferably using Hercules/Calibre tool set and be able to learn and understand design rules very quickly. Fast learner. Detail oriented (this is a must). Excellent communication. Team oriented person. Dedicated and hard working. Motivated to learn. Prior experience with tapeout flow. Understanding of flash memory layout and its hierarchy is a plus. Ability to understand and build flash memory arrays is a plus. Some exposure/ experience with pitch circuits layout is a plus. SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer. To Apply: |
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