In this position, the individual will be responsible for providing technical leadership in all aspects of ASIC design implementation; duties will include working closely with the ASIC design team in developing and modifying timing constraints for implementation. Complete ownership of Physical design implementation of the chip, Timing closure, IR/EM Analysis, and Timing/SI Signoff of the design. Ability to work with minimal supervision and act as technical lead to a team of engineers to accomplish set forth tasks is essential. He/She will be working closely with internal design team to help achieve timing closure on the chip. He/She will also drive IP integration strategies that ensure quality and avoid schedule surprises. The individual will influence and shape SanDisk's next generation physical design implementation capability to meet the demands of the design road map. Proactively work with EDA vendors to assess best in class capability and benchmark to establish compelling adoption arguments. The individual will provide technical coaching and mentoring to more junior team members and ensure the continued growth and success of the team.
This position requires a Masters Degree in Electrical Engineering or Computer Science with a minimum of 9 years of direct experience in design with at least 5 years in a technical lead role for Physical timing/SI optimization, Clock Tree design, Routing optimization, DFM, LVS and DRC. Proficiency in STA, Timing signoff off, writing, verifying modifying constraints both for timing signoff and for physical design and experience in PERL/TCL/Shell scripting is a must. Knowledge of Synthesis and DFT design tools and flow is a plus .The individual must have proven hands on experience leading the tape out of multiple large low power hierarchical 65nm/40nm designs. Expertise in Cadence, Synopsys flow is a must. Good verbal and written communication skills are required.
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills.
SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer.
This position requires a Masters Degree in Electrical Engineering or Computer Science with a minimum of 9 years of direct experience in design with at least 5 years in a technical lead role for Physical timing/SI optimization, Clock Tree design, Routing optimization, DFM, LVS and DRC. Proficiency in STA, Timing signoff off, writing, verifying modifying constraints both for timing signoff and for physical design and experience in PERL/TCL/Shell scripting is a must. Knowledge of Synthesis and DFT design tools and flow is a plus .The individual must have proven hands on experience leading the tape out of multiple large low power hierarchical 65nm/40nm designs. Expertise in Cadence, Synopsys flow is a must. Good verbal and written communication skills are required.
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills.
SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer.
To Apply:
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