| In this position, the individual will be responsible for leading test chip project. Co-lead derivate project. Develop cell-level, block-level, and full chip level DRC/LVS. Responsible optimization of various blocks including routing and via optimization. Responsible full chip activities including tape-out and ECO's after initial tape-out. Responsible test structure development including structures necessary for design rule development. Responsible of I/O circuits layout, ESD circuits layout, and pad layout. Work as part of a physical design team. Work closely with layout manager & layout project lead. Work with design engineer for layout requirements. This position requires an AA/AS degree with 6 months of certified layout training or equivalent experience and a minimum of 8 years related experience. BS/BA preferred. Excellent analog layout skill. Focus on analog layout placement matching and routing. Focus on charge pump, voltage generator. Experience in understanding parasitics and its impact to layout. Ability to optimize critical paths. Excellent performing manual routing and semi-auto routing. Good understanding of flash memory layout and its hierarchy. Be proficient in understanding layout and schematic hierarchy of existing chips and be able to make changes to existing chips and be able to at least take ownership of parts of the full chip. Good understand fundamental process steps. Independent thinking on assignment and able to come up with floor plan to optimize block placement and routing. Experience with Cadence "VLE, VXL, CCAR, PCELL" layout and schematic tools. Experience in Hercules/Calibre DRC/LVS verification tools. Experience in Unix environment. Needs to be able to debug DRC/LVS independently. Must be proficient in post layout processing, preferably using Hercules tool set and be able to learn and understand design rules very quickly. The individual should be a fast learner, detail oriented, excellent communicator and a team oriented person. Good layout and layout planning skills and be able to provide quality layout without much supervision. SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer. |
To Apply:
__._,_.___
.
__,_._,___
