| In this position, this individual will define architecture for 3D memory controllers from design specifications and proprietary protocols. Own and implement design and perform verification, synthesis, and back-end annotated timing closure. Support verification, circuit, and test groups throughout design cycle and silicon bring up. Strong knowledge of Verilog and scripting languages (PERL, TCL) is required. Familiarity with memory designs a plus. Requires BS/BA degree or equivalent with 5 or more years of related experience. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills. SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401(k), comprehensive insurance and tuition reimbursement. |
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